MT41J256M4 参数 Datasheet PDF下载

型号：	MT41J256M4
PDF下载：	下载PDF文件查看货源
内容描述：	DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 â 32 Meg x 4 x 8 banks MT41J128M8 â 16 Meg x 8 x 8 banks MT41J64M16 â 8 Meg x 16 x 8 banks]
分类和应用：	动态存储器双倍数据速率
文件页数/大小：	214 页 / 2938 K
品牌：	MICRON [ MICRON TECHNOLOGY ]

1Gb: x4, x8, x16 DDR3 SDRAM

RESET Operation

The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it

drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes

LOW, it must remain LOW for 1±±ns. During this time, the outputs are disabled, ODT

(R_TT) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to

RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized

as though a normal power-up was executed. All refresh counters on the DRAM are reset,

and data stored in the DRAM is assumed unknown after RESET# has gone LOW.

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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