1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 1 (MR1)
share the same ball. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is pro-
vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3
SDRAM configuration only and must be disabled via the mode register for the x4 and
x16 configurations.
On-Die Termination
ODT resistance RTT,nom is defined by MR1[9, 6, 2] (see Figure 55 (page 141)). The RTT
termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6, 8, or
12 and RZQ is 24±Ωꢁ
Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. RTT,nom termination is allowed any time after the DRAM is ini-
tialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT enabled (RTT(WR)) temporarily re-
places RTT,nom with RTT(WR)
.
The actual effective termination, RTT(EFF), may be different from the RTT targeted due to
nonlinearity of the termination. For RTT(EFF) values and calculations (see On-Die Termi-
nation (ODT) (page 193)).
The ODT feature is designed to improve signal integrity of the memory channel by ena-
bling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devi-
ces. The ODT input control pin is used to determine when RTT is turned on (ODTL on)
and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2].
Timings for ODT are detailed in On-Die Termination (ODT) (page 193).
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[0], as shown in Figure 55 (page 141).
Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as
a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory
modules adopted fly-by topology for the commands, addresses, control signals, and
clocks.
The fly-by topology benefits from a reduced number of stubs and their lengths. Howev-
er, fly-by topology induces flight time skews between the clock and DQS strobe (and
DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining
tDQSS, tDSS, and tDSH specifications without supporting write leveling in systems
which use fly-by topology-based modules. Write leveling timing and detailed operation
information is provided in Write Leveling (page 129).
POSTED CAS ADDITIVE Latency
POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus
efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL,
as shown in Figure 56 (page 144). MR1[4, 3] enable the user to program the DDR3
SDRAM with AL = ±, CL - 1, or CL - 2.
With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank prior to tRCD (MIN). The only restriction is
ACTIVATE to READ or WRITE + AL ≥ tRCD (MIN) must be satisfied. Assuming tRCD
(MIN) = CL, a typical application using this feature sets AL = CL - 1tCK = tRCD (MIN) - 1
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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143
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