1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 3 (MR3)
back to ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom is disabled, the
RTT,nom value will be High-Z. Special timing parameters must be adhered to when dy-
namic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,
and tADC.
Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT,nom) is disabled, dy-
namic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent of
one other. Dynamic ODT is not available during write leveling mode, regardless of the
state of ODT (RTT,nom). For details on dynamic ODT operation, refer to On-Die Termina-
tion (ODT) (page 193).
Mode Register 3 (MR3)
The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
This function is controlled via the bits shown in Figure 59 (page 140). The MR3 is pro-
grammed via the LOAD MODE command and retains the stored information until it is
programmed again or until the device loses power. Reprogramming the MR3 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR3 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time tMRD and tMOD before initiating a sub-
sequent operation.
Figure 59: Mode Register 3 (MR3) Definition
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
16 15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
0
Mode register 3 (MR3)
MPR READ Function
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
MPR MPR_RF
0
Mode Register
M2
MPR Enable
M15 M14
M1 M0
2
3
Mode register set (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
1
Normal DRAM operations
Dataflow from MPR
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Predefined pattern
Reserved
Reserved
Reserved
1. MR3[16 and 13:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
Notes:
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and ± determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 6± (page 148).
If MR3[2] is a ±, then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[±, 1]. If MR3[±, 1] is equal to ±±, then a prede-
fined read pattern for system calibration is selected.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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147
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