1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 1 (MR1)
If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa-
bled when entering SELF REFRESH operation and is automatically reenabled and reset
upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self re-
fresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until
it is reenabled and reset.
The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:
• ODT is not allowed to be used
• The output data is no longer edge-aligned to the clock
• CL and CWL can only be six clocks
When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see DLL Disable Mode (page 123)). Disabling
the DLL also implies the need to change the clock frequency (see Input Clock Frequen-
cy Change (page 120)).
Output Drive Strength
The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/0 (34Ω [NOM]) is the primary output
driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im-
pedance, an external precision resistor (RZQ) is connected between the ZQ ball and
V
SSQ. The value of the resistor must be 24±Ω rꢂꢉꢁ
The output impedance is set during initialization. Additional impedance calibration up-
dates do not affect device operation, and all data sheet timings and current specifica-
tions are met during an update.
To meet the 34Ω specification, the output drive strength must be set to 34Ω during initi-
alization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset proce-
dure.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 55
(page 141). When enabled (MR1[12] = ±), all outputs (DQ, DQS, DQS#) function when in
the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during IDD characterization of the READ current and during tDQSS margining (write
leveling) only.
TDQS Enable
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that
provides termination resistance (RTT) and may be useful in some system configurations.
TDQS is not supported in x4 or x16 configurations. When enabled via the mode register
(MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and TDQS#.
In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina-
tion resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not provided
by TDQS; thus, RON does not apply to TDQS and TDQS#. The TDQS and DM functions
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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