1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 0 (MR0)
quired to program the correct value of write recovery and is calculated by dividing tWR
(ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles) =
roundup (tWR [ns]/tCK [ns]).
Precharge Power-Down (Precharge PD)
The precharge PD bit applies only when precharge power-down mode is being used.
When MR±[12] is set to ±, the DLL is off during precharge power-down providing a low-
er standby current mode; however, tXPDLL must be satisfied when exiting. When
MR±[12] is set to 1, the DLL continues to run during precharge power-down mode to
enable a faster exit of precharge power-down mode; however, tXP must be satisfied
when exiting (see Power-Down Mode (page 183)).
CAS Latency (CL)
The CL is defined by MR±[6:4], as shown in Figure 53 (page 138). CAS latency is the de-
lay, in clock cycles, between the internal READ command and the availability of the first
bit of output data. The CL can be set to 5, 6, 0, 8, 9, or 1±. DDR3 SDRAM do not support
half-clock latencies.
Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-
tered at clock edge n, and the CAS latency is m clocks, the data will be available nomi-
nally coincident with clock edge n + m. on page through Table 52 (page 05) indicate the
CLs supported at various operating frequencies.
Figure 54: READ Latency
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
AL = 0, CL = 6
DQS, DQS#
DQ
DI
n
DI
DI
DI
DI
n + 1
n + 2
n + 3
n + 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Command
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
AL = 0, CL = 8
DQS, DQS#
DQ
DI
n
Transitioning Data
Don’t Care
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal tDQSCK and nominal tDSDQ.
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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