1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 1 (MR1)
Mode Register 1 (MR1)
The mode register 1 (MR1) controls additional functions and features not available in
the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration
only), DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE LEVELING, POSTED
CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are control-
led via the bits shown in Figure 55 (page 141). The MR1 register is programmed via the
MRS command and retains the stored information until it is reprogrammed, until RE-
SET# goes LOW, or until the device loses power. Reprogramming the MR1 register will
not alter the contents of the memory array, provided it is performed correctly.
The MR1 register must be loaded when all banks are idle and no bursts are in progress.
The controller must satisfy the specified timing parameters tMRD and tMOD before ini-
tiating a subsequent operation.
Figure 55: Mode Register 1 (MR1) Definition
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA2
Address bus
16 15 14 13 12 11 10
9
RTT
8
7
6
RTT
5
4
3
2
RTT
1
0
Mode register 1 (MR1)
1
1
1
1
WL
0
0
1
Q Off TDQS
ODS
AL
ODS DLL
0
0
0
M0
0
DLL Enable
Enable (normal)
Disable
M15 M14
Mode Register
M12
Q Off
M11
TDQS
0
0
1
1
0
1
0
1
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
1
0
1
Enabled
Disabled
0
1
Disabled
Enabled
M5 M1 Output Drive Strength
0
0
1
1
0
1
0
1
RZQ/6 (40ȍ [NOM])
RZQ/7 (34ȍ [NOM])
Reserved
2
3
M7
Write Leveling
Disable (normal)
Enable
RTT,nom (ODT)
Non-Writes
RTT,nom (ODT)
Writes
0
1
M9 M6 M2
RTT,nom disabled
RTT,nom disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
RZQ/4 (60ȍ [NOM]) RZQ/4 (60ȍ [NOM])
RZQ/2 (120ȍ [NOM]) RZQ/2 (120ȍ [NOM])
RZQ/6 (40ȍ [NOM]) RZQ/6 (40ȍ [NOM])
Additive Latency (AL)
Disabled (AL = 0)
AL = CL - 1
M4 M3
0
0
1
1
0
1
0
1
RZQ/12 (20ȍ [NOM])
RZQ/8 (30ȍ [NOM])
Reserved
n/a
n/a
AL = CL - 2
Reserved
Reserved
Reserved
Reserved
1. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to 0.
Notes:
2. During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available
for use.
3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values
are available for use.
DLL Enable/DLL Disable
The DLL may be enabled or disabled by programming MR1[±] during the LOAD MODE
command, as shown in Figure 55 (page 141). The DLL must be enabled for normal oper-
ation. DLL enable is required during power-up initialization and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debugging or evalua-
tion. Enabling the DLL should always be followed by resetting the DLL using the appro-
priate LOAD MODE command.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
141
2006 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
