1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 2 (MR2)
Figure 57: Mode Register 2 (MR2) Definition
A13
BA2 BA1 BA0
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode register 2 (MR2)
RTT(WR)
1
1
1
1
1
1
1
1
0
SRT ASR
CWL
1
0
0
0
0
0
0
0
0
M15 M14
Mode Register
M7 Self Refresh Temperature
M5 M4 M3
CAS Write Latency (CWL)
t
0
0
1
1
0
1
0
1
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
1
Normal (0°C to 85°C)
Extended (0°C to 95°C)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5 CK ( CK ꢋ2.5ns)
t
6 CK (2.5ns ! CK ꢋ1.875ns)
t
7 CK (1.875ns ! CK ꢋ1.5ns)
t
8 CK (1.5ns ! CK ꢋ1.25ns)
t
9 CK (1.25ns ! CK ꢋ1.07ns)
t
10 CK (1.071ns ! CK ꢋ0.938ns)
Auto Self Refresh
(Optional)
Dynamic ODT
M6
0
Reserved
Reserved
M10 M9
(RTT(WR) )
Disabled: Manual
Enabled: Automatic
0
0
1
1
0
1
0
1
R
TT(WR) disabled
1
RZQ/4
RZQ/2
Reserved
1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
Note:
CAS Write Latency (CWL)
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 50 (page 145)). The overall WRITE la-
tency (WL) is equal to CWL + AL (Figure 55 (page 141)).
Figure 58: CAS Write Latency
T11
T0
T1
T2
T6
T12
T13
T14
CK#
CK
ACTIVE n
WRITE n
NOP
NOP
NOP
NOP
NOP
NOP
Command
t
RCD (MIN)
DQS, DQS#
AL = 5
CWL = 6
DI
n
DI
DI
DI
DQ
n + 1
n + 2
n + 3
WL = AL + CWL = 11
Indicates break
in time scale
Transitioning Data
Don’t Care
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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145
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