1Gb: x4, x8, x16 DDR3 SDRAM
Write Leveling
Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 49 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T±), the memory controller should stop
driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memo-
ry controller to capture the applicable prime DQ state (at ~Tb±). The DQ balls become
undefined when DQS no longer remains LOW, and they remain undefined until tMOD
after the MRS command (at Te1).
The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the
t
DQS is no longer driving LOW. When ODT LOW satisfies IS, ODT must be kept LOW (at
~Tb±) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid com-
mand may be registered by the DRAM. Some MRS commands may be issued after tMRD
(at Td1).
Figure 49: Write Leveling Exit Procedure
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
CK#
CK
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
MR1
NOP
Valid
NOP
Valid
Valid
t
MRD
Address
Valid
tIS
t
MOD
ODT
t
AOF (MIN)
ODTLoff
R
t
R
DQS, R DQS#
TT
TT,nom
TT
t
AOF (MAX)
DQS, DQS#
R
TT(DQ)
t
WLO + WLOE
DQ
CK = 1
Indicates break
in time scale
Undefined Driving Mode
Transitioning
Don’t Care
1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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133
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