1Gb: x4, x8, x16 DDR3 SDRAM
Initialization
Figure 50: Initialization Sequence
T (MAX) = 200ms
VDD
See power-up
conditions
in the
initialization
VDDQ
sequence text,
set up 1
VTT
VREF
Stable and
valid clock
Tc0
Td0
Tb0
T1
T0
Ta0
tCK
Power-up
ramp
tVTD
CK#
CK
tCL
tCKSRX
tCL
tIOZ = 20ns
RESET#
tIS
T (MIN) = 10ns
Valid
Valid
CKE
ODT
tIS
NOP
Command
DM
MRS
MRS
MRS
MRS
ZQCL
Valid
Address
A10
Valid
Code
Code
Code
Code
Code
Code
Code
Code
Valid
Valid
A10 = H
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
BA[2:0]
DQS
DQ
RTT
tMRD
tMRD
tMOD
tXPR
tMRD
tZQinit
T = 200μs (MIN)
T = 500μs (MIN)
MR0 with
DLL reset
MR1 with
DLL enable
MR2
MR3
ZQ calibration
tDLLK
All voltage
supplies valid
and stable
DRAM ready for
external commands
Normal
operation
Indicates break
in time scale
Don’t Care
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
135
2006 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
