1Gb: x4, x8, x16 DDR3 SDRAM
Mode Registers
Mode Registers
Mode registers (MR±–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR±[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device
loses power.
Contents of a mode register can be altered by re-executing the MRS command. Even if
the user wants to modify only a subset of the mode register’s variables, all variables
must be programmed when the MRS command is issued. Reprogramming the mode
register will not alter the contents of the memory array, provided it is performed cor-
rectly.
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). After an MRS com-
mand has been issued, two parameters must be satisfied: tMRD and tMOD. The control-
ler must wait tMRD before initiating any subsequent MRS commands.
Figure 51: MRS to MRS Command Timing (tMRD)
T0
T1
T2
Ta0
Ta1
Ta2
CK#
CK
MRS1
NOP
NOP
NOP
NOP
MRS2
Command
tMRD
Address
CKE3
Valid
Valid
Indicates break
in time scale
Don’t Care
1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN)
must be satisfied, and no data bursts can be in progress.
2. tMRD specifies the MRS to MRS command minimum cycle time.
Notes:
3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Pow-
er-Down Mode (page 183)).
4. For a CAS latency change, tXPDLL timing must be met before any non-MRS command.
The controller must also wait tMOD before initiating any non-MRS commands (exclud-
ing NOP and DES). The DRAM requires tMOD in order to update the requested features,
with the exception of DLL RESET, which requires additional time. Until tMOD has been
satisfied, the updated features are to be assumed unavailable.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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136
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