OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
30, 45
RAS0#, RAS2#
Input
Row-Address Strobe: RAS# is used to clock-in the row-
address bits. Two RAS# inputs allow for one x72 bank or
two x36 banks.
28, 29, 46, 47, 112,
113, 130, 131
CAS0#-CAS7#
WE0#, WE2#
Input
Input
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles. Eight CAS#
inputs allow byte access control for any memory bank
configuration.
27, 48
Write Enable: WE# is the READ/WRITE control for the
DQ pins. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE#
is also LOW. If WE# goes LOW after CAS# goes LOW,
then the cycle is a LATE WRITE cycle. A LATE WRITE
cycle is generally used in conjunction with a READ cycle
to form a READ-MODIFY-WRITE cycle.
31, 44
OE0#, OE2#
Input
Input
Output Enable: OE# is the input/output control for the DQ
pins. These signals may be driven, allowing LATE WRITE
cycles.
33-38, 117-121
A0-A10
Address Inputs: These inputs are multiplexed and clocked
by RAS# and CAS#.
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89,91-95,
97-101, 103-104,
DQ0-DQ63
Input/
Output
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
139-142, 144, 149-151,
153-156, 158-161
21-22, 52-53, 105-106,
136-137
CB0-CB7
RFU
Input/Output
Check Bits.
42, 62, 111, 115,
125-126, 128, 132, 146
–
Reserved for Future Use: These pins should be left
unconnected.
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
VDD
Supply
Power Supply: +3.3V ±0.3V.
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
VSS
SDA
Supply
Input/Output
Input
Ground.
82
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out of
the presence-detect portion of the module.
83
SCL
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs. These pins are used to
configure the presence-detect device.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
6
MICRON [ MICRON TECHNOLOGY ]
