OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).
The SPD device will always respond with an acknowl-
edge after recognition of a start condition and its slave
address. If both the device and a write operation have been
selected, the SPD device will respond with an acknowledge
after the receipt of each subsequent eight-bit word. In the
read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition
is generated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave will
terminate further data transmissions and await the stop
condition to return to standby power mode.
SPD START CONDITION
All commands are preceded by the start condition, which
is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.
SPD STOP CONDITION
All communications are terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.
SCL
SDA
SCL
SDA
START
BIT
STOP
BIT
DATA STABLE
DATA
CHANGE
DATA STABLE
Figure 2
DEFINITION OF START AND STOP
Figure 1
DATA VALIDITY
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
ACKNOWLEDGE RESPONSE FROM RECEIVER
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
3
MICRON [ MICRON TECHNOLOGY ]
