OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
CAPACITANCE
MAX
PARAMETER
SYMBOL 16MB 32MB UNITS NOTES
Input Capacitance: A0-A10
CI1
CI2
CI3
CI4
CI5
CIO
51
39
39
17
6
96
67
67
24
6
pF
pF
pF
pF
pF
pF
2
2
2
2
2
2
Input Capacitance: WE0#, WE2#, OE0#, OE2#
Input Capacitance: RAS0#, RAS2#
Input Capacitance: CAS0#-CAS7#
Input Capacitance: SCL, SA0-SA2
Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA
10
10
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
-6
SYMBOL
MIN
MAX
UNITS
NOTES
t
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
AA
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AR
45
0
t
ASC
t
ASR
0
t
Column address to WE# delay time
Access time from CAS#
AWD
55
23
14
t
CAC
15
t
Column-address hold time
CAH
10
15
10
3
t
CAS# pulse width
CAS
10,000
t
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CHR
4
t
CLZ
25
15
t
CAS# precharge time
CP
10
t
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CPA
35
t
CRP
5
60
5
t
CSH
t
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
CSR
4
t
CWD
40
15
10
0
23
t
WRITE command to CAS# lead time
Data-in hold time
CWL
t
DH
22
22
t
Data-in setup time
DS
t
Output disable
OD
3
15
15
t
Output enable
OE
t
OE# hold time from WE# during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OEH
15
3
21
t
OFF
15
19, 25, 26
t
OE# setup prior to RAS# during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
ORD
0
t
PC
35
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
10
MICRON [ MICRON TECHNOLOGY ]
