OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
HIDDEN REFRESH CYCLE20, 27
(WE# = HIGH; OE# = LOW)
t
RC
t
t
t
RAS
RAS
RP
V
IH
RAS#
CAS#
V
IL
t
t
t
t
CRP
RCD
RSH
CHR
V
V
IH
IL
t
t
AR
RAD
t
t
t
t
CAH
ASR
RAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
t
AA
t
t
t
RAC
CAC
CLZ
t
OFF
V
V
IOH
IOL
DQ
OPEN
VALID DATA
OPEN
t
t
t
OD
OE
ORD
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
-6
-5*
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AA
25
30
OFF (EDO)
ORD
0
0
12
0
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AR
38
0
45
0
t
ASC
RAC
50
60
t
ASR
0
0
RAD (FPM)
RAD (EDO)
RAH
–
9
15
12
t
CAC
13
15
t
CAH
8
8
–
0
5
–
0
10
10
3
9
10
t
CHR
RAS
50
–
10,000
60
10,000
t
CLZ (FPM)
RC (FPM)
RC (EDO)
RCD (FPM)
RCD (EDO)
RP
110
104
20
t
CLZ (EDO)
0
84
–
t
CRP
5
t
OD (FPM)
–
12
12
–
3
15
15
15
15
11
30
13
14
t
OD (EDO)
0
40
t
OE
RSH
15
t
OFF (FPM)
–
3
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
28
MICRON [ MICRON TECHNOLOGY ]
