OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FAST/EDO-PAGE-MODE READ-WRITE CYCLE 27
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
t
t
t
t
NOTE 1
CSH
PC
PRWC
RSH
CAS
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
CWL
t
RCS
t
t
CWL
CWL
t
t
t
WP
WP
WP
t
t
t
t
t
AWD
AWD
AWD
CWD
t
CWD
CWD
V
V
IH
IL
WE#
t
t
t
AA
AA
AA
t
RAC
t
t
t
DH
DH
DH
t
t
CPA
CPA
t
t
t
DS
DS
DS
t
t
t
t
t
t
CAC
CLZ
CAC
CLZ
CAC
CLZ
V
V
IOH
IOL
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
DQ
OPEN
OPEN
D
D
D
D
D
D
t
t
t
OD
OD
OD
t
t
t
t
OE
OE
OE
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
-6
-5*
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
MAX
–
MIN
MAX
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AA
25
30
OD (FPM)
OE
–
3
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AR
38
0
45
0
12
15
t
ASC
OEH (EDO)
OEH (FPM)
PC (EDO)
PC (FPM)
PRWC (EDO)
PRWC (FPM)
RAC
8
–
10/12**
15
t
ASR
0
0
t
AWD (EDO)
42
–
49
55
20
–
25
t
AWD (FPM)
35
t
CAC
13
15
47
–
56
t
CAH
8
8
–
0
–
8
10
10
15
0
85
t
CAS (EDO)
10,000
–
10,000
10,000
50
60
t
CAS (FPM)
RAD (EDO)
RAD (FPM)
RAH
9
–
12
15
10
60
14
20
0
t
CLZ (EDO)
t
CLZ (FPM)
3
9
t
CP
10
RASP
50
11
–
125,000
125,000
t
CPA
28
35
RCD (EDO)
RCD (FPM)
RCS
t
CRP
5
38
–
5
t
CSH (EDO)
45
60
35
40
10
15
10
0
0
t
CSH (FPM)
RP
30
13
67
–
40
15
79
85
15
5
t
CWD (EDO)
28
–
RSH
t
CWD (FPM)
RWD (EDO)
RWD (FPM)
RWL
t
CWL (EDO)
8
t
CWL (FPM)
–
13
5
t
DH
8
WP (EDO)
WP (FPM)
t
DS
0
–
10
t
OD (EDO)
0
12
0
15
* EDO version only
**16MB DIMM
t
NOTE: 1. PC is for LATE WRITE cycles only.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
23
MICRON [ MICRON TECHNOLOGY ]
