OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EDO READ CYCLE
(with WE#-controlled disable)
V
IH
RAS#
CAS#
V
IL
t
CSH
t
t
t
t
t
CP
RCD
CAS
CAH
CRP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
ASC
ASR
ASC
V
V
IH
IL
ROW
COLUMN
COLUMN
ADDR
WE#
t
RCS
t
t
t
RCH
WPZ
RCS
V
V
IH
IL
t
t
t
t
AA
RAC
CAC
CLZ
t
t
WHZ
CLZ
V
V
OH
OL
DQ
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
t
t
AA
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OD
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AR
38
0
45
0
OE
12
15
t
t
ASC
RAC
50
60
t
t
ASR
0
0
RAD
9
9
12
10
14
0
t
t
CAC
13
15
RAH
t
t
CAH
8
8
10
10
0
RCD
11
0
t
t
CAS
10,000
10,000
RCH
t
t
CLZ
0
RCS
0
0
t
t
CP
8
10
5
WHZ
0
12
0
15
t
t
CRP
5
WPZ
10
10
t
CSH
38
45
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
26
MICRON [ MICRON TECHNOLOGY ]
