OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
READ-WRITE CYCLE 27
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
RWC
t
t
RP
RAS
V
V
IH
IL
RAS#
t
CSH
t
RSH
t
t
t
t
CAS
CRP
ASR
RCD
V
V
IH
IL
CAS#
ADDR
t
AR
t
t
t
t
CAH
RAD
ASC
RCS
t
t
ACH
RAH
V
V
IH
IL
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
AWD
V
V
IH
IL
WE#
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
V
IOH
IOL
VALID D
VALID D
DQ
OPEN
OPEN
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
-6
-5*
-6
SYMBOL
MIN
MAX
MIN
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
0
MAX
12
–
MIN
0
MAX
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AA
25
OD (EDO)
OD (FPM)
OE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ACH (EDO)
12
38
0
15
45
0
–
3
15
t
AR
12
15
t
ASC
OEH (EDO)
OEH (FPM)
RAC
8
–
10/12**
15
t
ASR
0
0
t
AWD (EDO)
42
–
49
55
50
60
t
AWD (FPM)
RAD (EDO)
RAD (FPM)
RAH
9
–
12
15
10
60
14
20
0
t
CAC
13
15
t
CAH
8
8
10
10
15
0
9
t
CAS (EDO)
10,000
–
10,000
10,000
RAS
50
11
–
10,000
10,000
t
CAS (FPM)
–
RCD (EDO)
RCD (FPM)
RCS
t
CLZ (EDO)
0
t
CLZ (FPM)
–
3
0
t
CRP
5
5
RP
30
13
116
–
40
15
140
155
79
85
15
5
t
CSH (EDO)
38
–
45
60
35
40
10
15
10
0
RSH
t
CSH (FPM)
RWC (EDO)
RWC (FPM)
RWD (EDO)
RWD (FPM)
RWL
t
CWD (EDO)
28
–
t
CWD (FPM)
67
–
t
CWL (EDO)
8
t
CWL (FPM)
–
13
5
t
DH
8
WP (EDO)
WP (FPM)
t
DS
0
–
10
* EDO version only
**16MB DIMM
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
22
MICRON [ MICRON TECHNOLOGY ]
