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MT18LD472AG-6 参数 Datasheet PDF下载

MT18LD472AG-6图片预览
型号: MT18LD472AG-6
PDF下载: 下载PDF文件 查看货源
内容描述: 2 , 4梅格X 72无缓冲DIMM的DRAM [2, 4 MEG x 72 NONBUFFERED DRAM DIMMs]
分类和应用: 动态存储器
文件页数/大小: 30 页 / 412 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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OBSOLETE  
2, 4 MEG x 72  
NONBUFFERED DRAM DIMMs  
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS  
(Notes: 1) (VDD = +3.3V ±0.3V)  
PARAMETER/CONDITION  
SYMBOL  
VDD  
VIH  
MIN  
MAX  
UNITS NOTES  
SUPPLY VOLTAGE  
3
3.6  
V
V
INPUT HIGH VOLTAGE: Logic 1; All inputs  
INPUT LOW VOLTAGE: Logic 0; All inputs  
OUTPUT LOW VOLTAGE: IOUT = 3mA  
INPUT LEAKAGE CURRENT: VIN = GND to VDD  
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD  
VDD × 0.7 VDD + 0.5  
VIL  
-1  
VDD × 0.3  
V
VOL  
ILI  
0.4  
10  
10  
30  
V
µA  
µA  
µA  
ILO  
STANDBY CURRENT:  
ISB  
SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%  
POWER SUPPLY CURRENT:  
SCL clock frequency = 100 KHz  
ICC  
2
mA  
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS  
(Notes: 1) (VDD = +3.3V ±0.3V)  
PARAMETER/CONDITION  
SYMBOL  
MIN  
0.3  
MAX  
UNITS  
µs  
NOTES  
t
SCL LOW to SDA data-out valid  
Time the bus must be free before a new transition can start  
Data-out hold time  
AA  
3.5  
t
BUF  
4.7  
µs  
t
DH  
300  
ns  
t
SDA and SCL fall time  
F
300  
100  
ns  
t
Data-in hold time  
HD:DAT  
0
4
4
µs  
t
Start condition hold time  
Clock HIGH period  
HD:STA  
µs  
t
HIGH  
t
µs  
Noise suppression time constant at SCL, SDA inputs  
Clock LOW period  
I
ns  
t
LOW  
4.7  
µs  
t
SDA and SCL rise time  
R
1
µs  
t
SCL clock frequency  
SCL  
100  
KHz  
ns  
t
Data-in setup time  
SU:DAT  
250  
4.7  
4.7  
t
Start condition setup time  
Stop condition setup time  
WRITE cycle time  
SU:STA  
µs  
t
SU:STO  
t
µs  
WR  
10  
ms  
28  
2, 4 Meg x 72 Nonbuffered DRAM DIMMs  
DM60.p65 – Rev. 6/98  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
1998, Micron Technology, Inc.  
14  
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