OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
NOTES
t
1. All voltages referenced to VSS.
tAA (tRAC and CAC no longer applied). With or
t
2. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
3. ICC is dependent on output loading. Specified values
are obtained with minimum cycle time and the
outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is ensured.
6. An initial pause of 100µs is required after power-up,
followed by eight RAS# REFRESH cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the tREF refresh
requirement is exceeded.
7. AC characteristics assume tT = 5ns for FPM and 2.5ns
for EDO.
8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
9. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
10. If CAS# = VIH, data output is High-Z.
11. If CAS# = VIL, data output may contain data from the
last valid READ cycle.
without the tRAD (MAX) limit, tAA, tRAC and CAC
must always be met.
t
t
18. Either RCH or RRH must be satisfied for a READ
cycle.
19. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
20. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21. LATE WRITE and READ-MODIFY-WRITE cycles
t
t
must have both OD and OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW after
tOEH is met. If CAS# goes HIGH prior to OE# going
back LOW, the DQs will remain open.
22. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
23. tWCS, tRWD, tAWD and CWD are not restrictive
t
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and CWD apply to
t
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
12. Measured with a load equivalent to two TTL gates
and 100pF and VOL = 0.8V and VOH = 2V.
the entire cycle. If tWCS < tWSC (MIN) and RWD ≥
t
13. Requires that tAA and RAC are not violated.
tRWD (MIN), tAWD ≥ tAWD (MIN) and CWD ≥
t
t
14. Requires that tAA and CAC are not violated.
tCWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW result in a
t
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
t
pulsed HIGH for CP.
16. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
LATE WRITE (OE#-controlled) cycle. WCS, tRWD,
tCWD and AWD are not applicable in a LATE
t
t
tRCD was greater than the specified RCD (MAX)
WRITE cycle.
t
limit, then access time was controlled exclusively by
24. Column address changed once each cycle.
25. The 3ns minimum parameter guaranteed by design.
26. With the FPM option, tOFF is determined by the first
RAS# or CAS# signal to transition HIGH. In compari-
son, tOFF on an EDO option is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
tCAC (tRAC [MIN] no longer applied). With or
t
without the tRCD (MAX) limit, tAA and CAC must
always be met.
17. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
t
tRAD was greater than the specified RAD (MAX)
limit, then access time was controlled exclusively by
27. Applies to both FPM and EDO modules.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
15
MICRON [ MICRON TECHNOLOGY ]
