OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
NOTES (continued)
28. The SPD EEPROM WRITE cycle time (tWR) is the
time from a valid stop condition of a write sequence
to the end of the EEPROM internal erase/ program
cycle. During the WRITE cycle, the EEPROM bus
interface circuit are disabled, SDA remains HIGH due
to pull-up resistor, and the EEPROM does not
respond to its slave address.
29. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
30. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse
width ≤ 10ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width ≤ 10ns, and the pulse
width cannot be greater than one third of the cycle
rate.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
16
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