OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
t
Access time from column address
Column-address setup to CAS# precharge
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
AA
25
30
t
ACH
12
38
0
15
45
0
t
AR
t
ASC
t
ASR
0
0
t
Column-address to WE# delay time
Access time from CAS#
AWD
42
49
23
14
t
CAC
13
15
t
Column-address hold time
CAS# pulse width
CAH
8
8
8
0
3
8
10
10
10
0
t
CAS
10,000
10,000
t
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CHR
4
t
CLZ
t
Data output hold after CAS# LOW
CAS# precharge time
COH
3
t
CP
10
15
t
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CPA
28
35
t
CRP
5
38
5
5
45
5
t
CSH
t
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
CSR
4
t
CWD
28
8
35
10
10
0
23
t
WRITE command to CAS# lead time
Data-in hold time
CWL
t
DH
8
22
22
t
Data-in setup time
DS
0
t
Output disable
OD
0
12
12
0
15
15
t
Output enable
OE
t
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OEH
8
10/12*
21
21
t
OE# HIGH hold time from CAS# HIGH
OE# HIGH pulse width
OEHC
5
5
4
0
0
10
5
ns
ns
ns
ns
ns
t
OEP
t
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
OES
5
t
OFF
12
50
0
15
60
19, 26
t
OE# setup prior to RAS#
during HIDDEN REFRESH cycle
ORD
0
t
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
PC
20
47
25
56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
t
PRWC
t
RAC
13
17
t
RAS# to column-address delay time
Row-address hold time
RAD
9
9
12
10
60
60
104
14
0
t
RAH
t
RAS# pulse width
RAS
50
50
84
11
0
10,000
10,000
t
RAS# pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
RASP
125,000
125,000
t
RC
t
RCD
16
18
t
READ command hold time (referenced to CAS#)
READ command setup time
RCH
t
RCS
0
0
t
Refresh period (2,048 cycles)
REF
32
32
t
RAS# precharge time
RP
30
40
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
12
MICRON [ MICRON TECHNOLOGY ]
