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MT16LD1664AG-5X 参数 Datasheet PDF下载

MT16LD1664AG-5X图片预览
型号: MT16LD1664AG-5X
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM模块 [DRAM MODULE]
分类和应用: 动态存储器
文件页数/大小: 27 页 / 518 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT16LD1664AG-5X的Datasheet PDF文件第7页浏览型号MT16LD1664AG-5X的Datasheet PDF文件第8页浏览型号MT16LD1664AG-5X的Datasheet PDF文件第9页浏览型号MT16LD1664AG-5X的Datasheet PDF文件第10页浏览型号MT16LD1664AG-5X的Datasheet PDF文件第12页浏览型号MT16LD1664AG-5X的Datasheet PDF文件第13页浏览型号MT16LD1664AG-5X的Datasheet PDF文件第14页浏览型号MT16LD1664AG-5X的Datasheet PDF文件第15页  
8, 16, 32 MEG x 64  
NONBUFFERED DRAM DIMMs  
EDO PAGE MODE  
AC ELECTRICAL CHARACTERISTICS  
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V 0.3V)  
ACCHARACTERISTICS  
PARAMETER  
-5  
-6  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
ns  
NOTES  
t
Access time from column address  
Column-addresssetuptoCAS#  
prechargeduringwrites  
AA  
25  
30  
t
ACH  
12  
15  
t
Column-addressholdtime(referencedtoRAS#)  
Column-addresssetuptime  
Row-addresssetuptime  
Column address to WE# delay time  
Access time from CAS#  
Column-addressholdtime  
CAS#pulsewidth  
CAS#holdtime(CBRRefresh)  
CAS# to output in Low-Z  
Data output hold after CAS# LOW  
CAS#prechargetime  
Access time from CAS# precharge  
CAS# to RAS# precharge time  
CAS# hold time  
CAS# setup time (CBR Refresh)  
CAS# to WE# delay time  
WRITE command to CAS# lead time  
Data-in hold time  
AR  
38  
0
0
45  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
ASC  
t
ASR  
t
AWD  
42  
49  
23  
14  
t
CAC  
13  
15  
t
CAH  
8
8
8
0
3
8
10  
10  
10  
0
3
10  
t
CAS  
10,000  
10,000  
t
CHR  
4
t
CLZ  
t
COH  
t
CP  
15  
t
CPA  
CRP  
28  
35  
t
5
38  
5
5
45  
5
t
CSH  
t
CSR  
4
t
CWD  
CWL  
30  
8
8
0
0
35  
10  
10  
0
23  
t
t
DH  
DS  
22  
22  
t
Data-in setup time  
Outputdisable  
Outputenable  
OE# hold time from WE# during  
READ-MODIFY-WRITEcycle  
t
OD  
OE  
12  
12  
0
15  
15  
t
t
OEH  
8
10  
t
OE# HIGH hold time from CAS# HIGH  
OE#HIGHpulsewidth  
OE# LOW to CAS# HIGH setup time  
Output buffer turn-off delay  
OE# setup prior to RAS#  
duringHIDDENREFRESHcycle  
OEHC  
5
5
4
0
0
10  
5
5
0
0
ns  
ns  
ns  
ns  
ns  
t
OEP  
t
OES  
t
OFF  
12  
50  
15  
60  
19, 27  
19  
t
ORD  
t
EDO-PAGE-MODEREADorWRITEcycletime  
EDO-PAGE-MODEREAD-WRITEcycletime  
Access time from RAS#  
RAS# to column-address delay time  
Row-addressholdtime  
PC  
20  
47  
25  
56  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
PRWC  
t
RAC  
13  
17  
t
RAD  
9
9
12  
10  
60  
60  
104  
14  
0
t
RAH  
t
RAS#pulsewidth  
RAS  
50  
50  
84  
11  
0
10,000  
125,000  
10,000  
125,000  
t
RAS#pulsewidth(EDOPAGEMODE)  
Random READ or WRITE cycle time  
RAS# to CAS# delay time  
READcommandholdtime(referencedtoCAS#)  
READcommandsetuptime  
RASP  
t
RC  
RCD  
RCH  
RCS  
t
16  
18  
t
t
0
0
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs  
DM78.p65 Rev. 2/99  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
©1999,MicronTechnology,Inc.  
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