8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
NOTES
1. All voltages referenced to VSS.
19.tOFF (MAX) defines the time at ꢀhich the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
2±.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The maximum current ratings are based ꢀith the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half ꢀhen used in the x32
mode.
22.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
2. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
3. ICC is dependent on output loading and cycle
rates. Specified values are obtained ꢀith minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at ꢀhich proper operation over
the full temperature range is ensured.
6. An initial pause of 1±±µs is required after poꢀer-
up, folloꢀed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR ꢀith WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle ꢀake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 2ns for -5 and 2.5ns
for -6.
8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured betꢀeen VIH and VIL (or betꢀeen VIL
and VIH).
9. In addition to meeting the transition rate
specification, all input signals must transit betꢀeen
VIH and VIL (or betꢀeen VIL and VIH) in a mono-
tonic manner.
1±.If CAS# and RAS# = VIH, data output is High-Z.
11.If CAS# = VIL, data output may contain data from
the last valid READ cycle.
23.tWCS, RWD, AWD and CWD are not restrictive
t
t
t
t
operating parameters. WCS applies to EARLY
WRITE cycles. If tWCS > tWCS (MIN), the cycle is
an EARLY WRITE cycle and the data output ꢀill
remain an open circuit throughout the entire
t
t
t
cycle. RWD, AWD and CWD define READ-
MODIFY-WRITE cycles. Meeting these limits
alloꢀs for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW result in a
t
t
LATE WRITE (OE#-controlled) cycle. WCS, RWD,
tCWD and AWD are not applicable in a LATE
t
WRITE cycle.
12.Measured ꢀith a load equivalent to tꢀo TTL gates
and 1±±pF and VOL = ±.8V and VOH = 2V.
24.Column address changed once each cycle.
25.The 3ns minimum parameter guaranteed by
design.
t
13.Requires that tAA and CAC are not violated.
t
t
14.Requires that AA and RAC are not violated.
15.If CAS# is LOW at the falling edge of RAS#,
output data ꢀill be maintained from the previous
cycle. To initiate a neꢀ cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for tCP.
16.The tRCD (MAX) limit is no longer specified. tRCD
(MAX) ꢀas specified as a reference point only. If
tRCD ꢀas greater than the specified tRCD (MAX)
limit, then access time ꢀas controlled exclusively
26.Measured ꢀith the specified current load and
1±±pF.
27.tOFF on an EDO module is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
28.The SPD EEPROM WRITE cycle time (tWR) is the
time from a valid stop condition of a ꢀrite
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit are disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
29.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
possible.
t
by CAC (tRAC [MIN] no longer applied). With or
t
t
t
ꢀithout the RCD (MAX) limit, AA and CAC
must alꢀays be met.
17.The tRAD (MAX) limit is no longer specified. tRAD
(MAX) ꢀas specified as a reference point only. If
tRAD ꢀas greater than the specified RAD (MAX)
t
limit, then access time ꢀas controlled exclusively
3±. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse
ꢀidth ≤ 1±ns, and the pulse ꢀidth cannot be
greater than one third of the cycle rate. VIL
undershoot: VIL (MIN) = -2V for a pulse ꢀidth ≤
1±ns, and the pulse ꢀidth cannot be greater than
one third of the cycle rate.
t
t
by AA (tRAC and CAC no longer applied). With
t
t
t
or ꢀithout the RAD (MAX) limit, AA, RAC and
tCAC must alꢀays be met.
18.Either tRCH or tRRH must be satisfied for a READ
cycle.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
14
MICRON [ MICRON TECHNOLOGY ]
