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M25PX16SOVZM6TP 参数 Datasheet PDF下载

M25PX16SOVZM6TP图片预览
型号: M25PX16SOVZM6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 65 页 / 1418 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Instructions  
M25PX16  
6.12  
Dual Input Fast Program (DIFP)  
The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP)  
instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of  
only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth  
compared to the Page Program (PP) instruction.  
The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low,  
followed by the instruction code, three address bytes and at least one data byte on Serial  
Data input (DQ0).  
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes  
beyond the end of the current page are programmed from the start address of the same  
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)  
must be driven Low for the entire duration of the sequence.  
The instruction sequence is shown in Figure 19.  
If more than 256 bytes are sent to the device, previously latched data are discarded and the  
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less  
than 256 data bytes are sent to device, they are correctly programmed at the requested  
addresses without having any effects on the other bytes in the same page.  
For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP)  
instruction to program all consecutive targeted bytes in a single sequence rather to using  
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see  
Table 18: AC characteristics).  
Chip Select (S) must be driven High after the eighth bit of the last data byte has been  
latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed.  
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose  
duration is t ) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,  
PP  
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The  
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is  
completed. At some unspecified time before the cycle is completed, the Write Enable Latch  
(WEL) bit is reset.  
A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the  
Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.  
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