Instructions
M25PX16
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Figure 15. Dual Output Fast Read instruction sequence
S
Mode 3
Mode 2
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24-bit address
DQ0
DQ1
23 22 21
3
2
1
0
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy byte
DQ0
DQ1
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DATA OUT 1 DATA OUT 2 DATA OUT 3
DATA OUT n
7
5
3
1
7
5
3
1
7
5
3
1
7
5
1
3
MSB
MSB
MSB
MSB
MSB
ai13574
1. A23 to A22 are Don't care.
6.9
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency f , during the falling edge of
C
Serial Clock (C).
The instruction sequence is shown in Figure 16.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
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MICRON [ MICRON TECHNOLOGY ]
