M25PX16
Instructions
Figure 21. How to permanently lock the 64 OTP bytes
64 data bytes
OTP Control byte
Byte Byte Byte
Byte Byte
63 64
0
1
2
X
X
X
X
bit 3 bit 2 bit 1 bit 0 When bits 3, 2, 1, and 0 = 0,
the 64 OTP bytes become
READ only
Bit 4 to bit 7 are NOT
programmable
ai13587
6.14
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is
shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the data byte
has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not
executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than t
minimum value.
SHSL
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 22. Write to Lock Register (WRLR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Lock Register
C
Instruction
24-Bit Address
In
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
DQ0
MSB
AI13740
39/65
MICRON [ MICRON TECHNOLOGY ]
