Instructions
M25PX16
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
To lock the OTP memory:
Bit 0 of the OTP control byte, that is byte 64, (see Figure 21) is used to permanently lock the
OTP memory array.
When bits 3, 2, 1 and 0 of byte 64 = ’1’, the 64 bytes of the OTP memory array can be
programmed.
When bits 3, 2, 1, and 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are
read-only and cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’.
Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP
memory array become read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in
progress is rejected without having any effect on the cycle that is in progress.
Figure 20. Program OTP (POTP) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
Data byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
DQ0
S
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
Data byte 3
Data byte n
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
DQ0
MSB
MSB
MSB
AI13575
1. A23 to A7 are Don't care.
2. 1 ≤ n ≤ 65
38/65
MICRON [ MICRON TECHNOLOGY ]
