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M25PX16SOVZM6TP 参数 Datasheet PDF下载

M25PX16SOVZM6TP图片预览
型号: M25PX16SOVZM6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位,双I / O , 4 KB的界别分组擦除,串行闪存与75 MHz的SPI总线接口 [16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 65 页 / 1418 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Instructions  
M25PX16  
instruction issued while an Erase, Program or Write cycle is in progress, is rejected without  
having any effect on the cycle that is in progress.  
Figure 17. Read OTP (ROTP) instruction and data-out sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31  
C
Instruction  
24-bit address  
23 22 21  
3
2
1
0
DQ0  
DQ1  
High Impedance  
S
C
47  
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46  
Dummy byte  
7
6
5
4
3
2
0
1
DQ0  
DQ1  
DATA OUT n  
DATA OUT 1  
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB  
MSB  
MSB  
AI13573  
1. A23 to A7 are Don't care.  
2. 1 n 65.  
6.11  
Page Program (PP)  
The Page Program (PP) instruction allows bytes to be programmed in the memory  
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction  
must previously have been executed. After the Write Enable (WREN) instruction has been  
decoded, the device sets the Write Enable Latch (WEL).  
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by  
the instruction code, three address bytes and at least one data byte on Serial Data input  
(DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that  
goes beyond the end of the current page are programmed from the start address of the  
same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip  
Select (S) must be driven Low for the entire duration of the sequence.  
The instruction sequence is shown in Figure 18.  
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