256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. The synchronous burst sequence for all burst lengths, as well as
the effect of the Burst Wrap (BW) setting are shown here.
Table 21: Burst Sequence Word Ordering
Start
Address
(DEC)
Burst
Wrap
(RCR.3)
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] =
0b001)
8-Word Burst
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
(BL[2:0] = 0b010)
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
⋮
0
1
0
0
0
0
0
0
0
0
⋮
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4…14-15
1-2-3-4-5…15-0
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
⋮
2
2-3-4-5-6…15-0-1
3-4-5-6-7…15-0-1-2
4-5-6-7-8…15-0-1-2-3
5-6-7-8-9…15-0-1-2-3-4
6-7-8-9-10…15-0-1-2-3-4-5
7-8-9-10…15-0-1-2-3-4-5-6
⋮
3
4
5
6
7
⋮
⋮
14
15
⋮
0
0
⋮
14-15-0-1-2…12-13
15-0-1-2-3…13-14
⋮
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
⋮
⋮
⋮
0
1
1
1
1
1
1
1
1
⋮
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
⋮
0-1-2-3-4…14-15
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
7-8-9-10-11…21-22
⋮
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
⋮
1
2
3
4
5
6
7
⋮
⋮
14
15
1
1
14-15-16-17-18…28-29
15-16-17-18-19…29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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