256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15 =0). The WAIT signal is only deasserted when data is valid on the bus. When the
device is operating in synchronous non-array read mode, such as read status, read ID,
or read CFI, the WAIT signal is also deasserted when data is valid on the bus. WAIT be-
havior during synchronous non-array reads at the end of word line works correctly only
on the first data access. When the device is operating in asynchronous page mode,
asynchronous single word read mode, and all write operations, WAIT is set to a deasser-
ted state as determined by RCR.10.
Table 20: WAIT Functionality Table
Condition
WAIT
High-Z
Active
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
1, 2
1
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Active
1
Active
1
Deasserted
High-Z
1
1, 2
1. Active means that WAIT is asserted until data becomes valid, then desserts.
2. When OE# = VIH during writes, WAIT = High-Z.
Notes:
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchro-
nous burst reads. WAIT can be asserted either during or one data cycle before valid data
is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid
data (default). When WD is cleared, WAIT is deasserted during valid data.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
48
© 2013 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
