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JS28F256P30TFE 参数 Datasheet PDF下载

JS28F256P30TFE图片预览
型号: JS28F256P30TFE
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB和512MB (256 / 256MB ) , P30-65nm [256Mb and 512Mb (256Mb/256Mb), P30-65nm]
分类和应用:
文件页数/大小: 95 页 / 1351 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb and 512Mb (256Mb/256Mb), P30-65nm  
Registers  
Locking the OTP Registers  
Each OTP Register can be locked by programming its respective lock bit in the Lock  
Register. To lock an OTP Register, program the corresponding bit in the Lock Register by  
issuing the Program Lock Register command, followed by the desired Lock Register da-  
ta. The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for regis-  
ter 1. These addresses are used when programming the lock registers.  
Bit 0 of Lock Register 0 is already programmed during the manufacturing process, lock-  
ing the lower half segment of the first 128-bit OTP Register. Bit 1 of Lock Register 0 can  
be programmed by user to the upper half segment of the first 128-bit OTP Register.  
When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’ such that  
the data programmed is 0xFFFD.  
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each bit  
of Lock Register 1 corresponds to a specific 128-bit OTP Register. Programming a bit in  
Lock Register 1 locks the corresponding 128-bit OTP Register; e.g., programming LR1.0  
locks the corresponding OTP Register 1.  
Note: After being locked, the OTP Registers cannot be unlocked.  
PDF: 09005aef84566799  
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2013 Micron Technology, Inc. All rights reserved.  
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