256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length
accesses wrap within the selected word-length boundaries or cross word-length boun-
daries. When BW is set, burst wrapping does not occur (default). When BW is cleared,
burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may
occur when the burst sequence crosses its first device-row (16-word) boundary. If the
burst sequence’s start address is 4-word aligned, then no delay occurs. If the start ad-
dress is at the end of a 4-word boundary, the worst case output delay is one clock cycle
less than the first access Latency Count. This delay can take place only once, and
doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT in-
forms the system of this delay when it occurs.
Burst Length
The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or con-
tinuous.
Continuous-burst accesses are linear only, and do not wrap within any word length
boundaries. When a burst cycle begins, the device outputs synchronous burst data until
it reaches the end of the “burstable” address space.
One-Time-Programmable (OTP) Registers
The device contains 17 one-time programmable (OTP) registers that can be used to im-
plement system security measures and/or device identification. Each OTP register can
be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Micron factory with a unique 64-bit number.
The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers, are blank.
Users can program these registers as needed. Once programmed, users can then lock
the OTP Register(s) to prevent additional bit programming (see the OTP Register Map
figure).
The OTP Registers contain one-time programmable (OTP) bits; when programmed, PR
bits cannot be erased. Each OTP Register can be accessed multiple times to program in-
dividual bits, as long as the register remains unlocked.
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is pro-
grammed, the associated OTP Register can only be read; it can no longer be program-
med. Additionally, because the Lock Register bits themselves are OTP, when program-
med, Lock Register bits cannot be erased. Therefore, when a OTP Register is locked, it
cannot be unlocked.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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