256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
Table 18: Latency Count and Frequency Support
Latency Count Settings
5 (TSOP); 4 (Easy BGA)
5 (Easy BGA)
Frequency Support (MHz)
≤ 40
≤ 52
Figure 14: Example Latency Count Setting Using Code 3
t
Data
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:1]
Code 3
High-Z
D[15:0]
Data
R103
End of Word Line (EOWL) Considerations
End of Wordline (EOWL) WAIT states can result when the starting address of the burst
operation is not aligned to a 16-word boundary; that is, A[3:0] of start address does not
equal 0x0. The End of Wordline Timing Diagram illustrates the end of wordline WAIT
state(s) that occur after the first 16-word boundary is reached. The number of data
words and the number of WAIT states is summarized in the End of Wordline Data and
WAIT State Comparison table for both P30-130nm and P30-65nm devices.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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