256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to
determine this value and the First Access Latency Count figure shows the data output
latency for the different settings of LC. The minimum Latency Count for P30-65nm
would be Code 4 based on the Max Clock frequency specification of 52 MHz, and there
will be zero WAIT States when bursting within the word line. Refer to End of Word Line
Considerations for more information on EOWL, and the Latency Count and Frequency
Support table for latency code settings.
Figure 13: First Access Latency Count
CLK [C]
Valid
Address [A]
Address
ADV# [V]
Code 0 (Reserved
)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQ[15:0] [D/Q]
Output
Output
Output
Output
Output
Output
Output
Output
Code
1
Valid
Valid
Valid
Valid
Valid
Valid
Valid
(Reserved
)
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
Output
Output
Output
Output
Output
Output
Output
Code
Code
2
Valid
Valid
Valid
Valid
Valid
Valid
Output
Output
Output
Output
Output
Output
3
Valid
Valid
Valid
Valid
Valid
Output
Output
Output
Output
Output
Code
Code
Code
Code
4
5
6
7
Valid
Valid
Valid
Valid
Output
Output
Output
Output
Valid
Valid
Valid
Output
Output
Output
Valid
Valid
Output
Output
Valid
Output
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
45
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