256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
Figure 16: OTP Register Map
0x109
128-bit OTP
Register 16
User Programmable
0x102
0x91
128-bit OTP
Register 1
User Programmable
Lock Register 1
0x8A
0x89
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x88
64-bit Segment
User Programmable
128-bit OTP
Register 0
0x85
0x84
64-bit Segment
Factory Programed
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reading the OTP Registers
The OTP Registers can be read from OTP-RA address. To read the OTP Register, first is-
sue the Read Device Identifier command at OTP-RA address to place the device in the
Read Device Identifier state. Next, perform a read operation using the address offset
corresponding to the register to be read. The Device Identifier Information table shows
the address offsets of the OTP Registers and Lock Registers. PR data is read 16 bits at a
time.
Programming the OTP Registers
To program an OTP Register, first issue the Program OTP Register command at the pa-
rameter’s base address plus the offset of the desired OTP Register location. Next, write
the desired OTP Register data to the same OTP Register address.
The device programs the 64-bit and 128-bit user-programmable OTP Register data 16
bits at a time. Issuing the Program OTP Register command outside of the OTP Register’s
address space causes a program error (SR.4 set). Attempting to program a locked OTP
Register causes a program error (SR.4 set) and a lock error (SR.1 set).
Note:
When programming the OTP bits in the OTP registers for a Top Parameter Device, the
following upper address bits must also be driven properly: A[Max:17] driven high (VIH
for TSOP and Easy BGA packages, and A[Max:16] driven high (VIH) for QUAD+ SCSP.
)
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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