P30-65nm SBC
Table 25: AC Read Specifications (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
(5)
Synchronous Specifications
R301
R302
R303
t
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
9
9
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVCH/L
t
VLCH/L
t
-
1,6
ELCH/L
Easy BGA/QUAD+
TSOP
17
20
-
R304
t
t
CLK to output valid
CHQV / CLQV
-
Easy BGA/QUAD+
TSOP
3
5
10
-
1,6
1,6
1,4,6
1,6
1,6
1
R305
R306
R307
R311
R312
t
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
CHQX
-
t
-
CHAX
Easy BGA/QUAD+
TSOP
17
20
-
t
CHTV
-
t
CLK Valid to ADV# Setup
WAIT Hold from CLK
3
3
5
CHVL
CHTX
Easy BGA/QUAD+
TSOP
-
1,6
1,6
t
-
Notes:
1.
See Figure 16, “AC Input/Output Reference Waveform” on page 48 for timing measurements and
max allowable input slew rate.
2.
3.
4.
5.
6.
OE# may be delayed by up to t
Sampled, not 100% tested.
Address hold in synchronous burst read mode is t
– t
after CE#’s falling edge without impact to t
ELQV
GLQV ELQV.
or t
, whichever timing specification is satisfied first.
VHAX
CHAX
Synchronous burst read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
Figure 19: Asynchronous Single-Word Read (ADV# Low)
R1
R2
Address[A]
ADV#[V]
R3
R8
CE# [E]
R4
R9
OE# [G]
R15
R17
WAIT [T]
R7
R6
Data [D/Q]
R5
RST# [P]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
51
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
