P30-65nm SBC
Figure 20: Asynchronous Single-Word Read (ADV# Latch)
R1
R2
Address[A]
A[3:1][A]
R101
R105
R106
R104
ADV#[V]
CE#[E]
R3
R8
R9
R4
OE#[G]
WAIT[T]
R15
R17
R7
R6
R10
Data[D/Q]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Figure 21: Asynchronous Page-Mode Read Timing
R2
A[Max:4] [A]
A[3:1]
Valid Address
R10
R10
R10
R10
0
1
2
F
R101
R105
R106
ADV# [V]
CE# [E]
R3
R8
R4
R9
OE# [G]
WAIT [T]
R6
R108
Q2
R108
Q3
R108
Q 8
R13
DATA[D/Q]
Q1
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
52
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
