P30-65nm SBC
Figure 24: Synchronous Burst-Mode Four-Word Read Timing
R302
R301
R306
CLK [C]
Address [A]
ADV# [V]
R2
R101
A
R105
R102
R106
R303
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R9
R15
R307
R17
R4
R304
R305
Q0
R7
R304
R10
Data [D/Q]
Q1
Q2
Q3
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10=0, WAIT asserted low).
15.4
AC Write Specifications
Table 26: AC Write Specifications (Sheet 1 of 2)
Num
W1
Symbol
Parameter
Min
Max
Unit
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RST# high recovery to WE# low
CE# setup to WE# low
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
1,2,4
1,2,12
PHWL
ELWL
W2
W3
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
50
50
50
0
WLWH
DVWH
AVWH
WHEH
WHDX
WHAX
WHWL
VPWH
QVVL
W4
W5
W6
1,2
W7
0
W8
0
W9
20
200
0
1,2,5
W10
W11
W12
W13
W14
W16
VPP setup to WE# high
VPP hold from Status read
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
1,2,3,7
0
QVBL
1,2,3,7
200
0
BHWH
WHGL
WHQV
1,2,9
WE# high to read valid
t
+ 35
1,2,3,6,10
AVQV
Write to Asynchronous Read Specifications
W18
t
WE# high to Address valid
0
-
ns
1,2,3,6,8
WHAV
Datasheet
54
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
