P30-65nm SBC
15.0
AC Characteristics
15.1
AC Test Conditions
Figure 16: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
IO_REF.WMF
Note: AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5ns. Worst case speed occurs at V = VCCMin.
CC
Figure 17: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Notes:
1.
2.
See the following table for component values.
Test configuration component value for worst case speed conditions.
3.
C includes jig capacitance
L
.
Table 23: Test Configuration Component Value for Worst Case Speed Conditions
Test Configuration
VCCQ Min Standard Test
C
(pF)
L
30
Datasheet
48
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
