P30-65nm SBC
15.3
AC Read Specifications
Table 25: AC Read Specifications (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
Easy BGA/QUAD+
TSOP
65
75
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
R1
R2
R3
t
Read cycle time
AVAV
-
Easy BGA/QUAD+
TSOP
65
75
65
75
25
150
-
-
-
t
Address to output valid
AVQV
-
Easy BGA/QUAD+
TSOP
-
-
t
CE# low to output valid
ELQV
-
-
R4
R5
R6
R7
R8
R9
t
t
OE# low to output valid
-
1,2
1
GLQV
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
-
PHQV
t
0
0
-
1,3
1,2,3
ELQX
GLQX
EHQZ
GHQZ
t
t
-
20
15
t
-
1,3
Output hold from first occurring address, CE#, or OE#
change
R10
t
0
-
ns
OH
R11
R12
R13
R15
R16
R17
t
CE# pulse width high
17
-
-
ns
ns
ns
ns
ns
ns
EHEL
1
t
CE# low to WAIT valid
CE# high to WAIT high-Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
17
20
17
-
ELTV
t
-
1,3
1
EHTZ
t
t
-
GLTV
GLTX
0
-
1,3
t
20
GHTZ
Latching Specifications
R101
R102
t
Address setup to ADV# high
CE# low to ADV# high
10
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVVH
t
ELVH
Easy BGA/QUAD+
65
75
-
R103
t
ADV# low to output valid
TSOP
1
VLQV
-
R104
R105
R106
R108
R111
t
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
10
10
9
VLVH
VHVL
VHAX
t
-
t
-
1,4
1
t
-
25
-
APA
t
RST# high to ADV# high
30
PHVH
Clock Specifications
Easy BGA/QUAD+
-
-
52
40
-
MHz
MHz
ns
R200
R201
fCLK
CLK frequency
TSOP
Easy BGA/QUAD+
19.2
25
5
tCLK
CLK period
TSOP
-
ns
1,3,5,6
Easy BGA/QUAD+
CLK high/low time
TSOP
-
ns
R202
R203
tCH/CL
9
-
ns
tFCLK/RCLK
CLK fall/rise time
0.3
3
ns
Datasheet
50
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
