P30-65nm SBC
Table 26: AC Write Specifications (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Write to Synchronous Read Specifications
W19
W20
t
t
WE# high to Clock valid
WE# high to ADV# high
19
19
-
-
ns
ns
WHCH/L
WHVH
1,2,3,6,10
Write Specifications with Clock Active
W21
W22
t
t
ADV# high to WE# low
Clock high to WE# low
-
-
27
27
ns
ns
VHWL
CHWL
1,2,3,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
or t
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
WLWH
ELEH
(whichever occurs first). Hence, t
= t
= t
= t
.
ELWH
WLWH
EHEL
ELEH
WLEH
5.
Write pulse width high (t
(whichever occurs last). Hence, t
or t
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
WHWL
= t
= t
= t
).
EHWL
WHWL
EHEL
WHEL
6.
7.
8.
t
or t
must be met when transiting from a write cycle to a synchronous burst read.
WHVH
WHCH/L
VPP and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20ns.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
9.
10.
11.
12.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation
to this timing specification.
Figure 25: Write-to-Write Timing
W5
W8
W5
W8
Address[A]
W2
W6
W2
W6
CE# [E]
W3
W9
W3
WE# [W]
OE# [G]
W4
W7
W4
W7
Data [D/Q]
W1
RST# [P]
Datasheet
55
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
