P30-65nm SBC
11.0
Register
When non-array reads are performed in asynchronous page mode only the first data is
valid and all subsequent data are undefined. When a non-array read operation occurs
as synchronous burst mode, the same word of data requested will be output on
successive clock edges until the burst length requirements are satisfied.
11.1
Status Register (SR)
The Status Register provides the ready/busy information of the device, as well as the
error information about the program, erase, VPP and block-locked operations. please
refer to Section 7.4, “Read Status Register” on page 23 and Section 7.5, “Clear Status
Register” on page 23 for detail operations.
Table 12: Status Register Description
Status Register (SR)
Default Value = 0x80
Device
Ready
Status
Erase Suspend
Program
Suspend Status
Block-Locked
BEFP Write
Status
Erase Status Program Status
VPP Status
1
Status
Status
DRS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
BWS
0
Bit
Name
Description
0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
7
Device Ready Status
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
6
5
Erase Suspend Status
Erase Status
SR.5
SR.4
Description
Command
Sequence
Error
0
0
1
1
0
1
0
1
Program or Erase operation successful.
Program error - operation aborted.
Erase error - operation aborted.
4
Program Status
VPP Status
Command sequence error - command aborted.
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < V during program or erase operation.
3
2
1
PPLK
0 = Program suspend not in effect.
1 = Program suspend in effect.
Program Suspend Status
Block-Locked Status
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
2
0
BEFP Write Status
1 = BEFP in-progress.
1. Always clear the Status Register before resuming erase operations afer an Erase Suspend command; this prevents ambiguity in
Status Register information. For example, if a command sequence error occurs during an erase suspend state, the Status
Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible
errors during the erase operation cannot be deteted via the Stauts Register because it contains the previous error status.
2. BEFP mode is only valid in array.
11.2
Read Configuration Register (RCR)
The RCR is a 16-bit read/write register used to select bus-read mode (synchronous or
asynchronous), and to configure synchronous burst read characteristics of the device.
To modify RCR settings, use the Configure Read Configuration Register command (see
Section 6.2, “Device Command Bus Cycles” on page 20).
Datasheet
34
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
