P30-65nm SBC
ADV# can remain asserted throughout the burst access, in which case the address is
latched on the next valid CLK edge while ADV# is asserted. Once OE# is asserted, the
the first word is driven onto DQ[15:0] on the next valid CLK edge after initial access
latency delay (see Section 11.2.2, “Latency Count (RCR[13:11])” on page 36).
Subsequent data is output on valid CLK edges following a minimum delay TCHQV (see
Table 25, “AC Read Specifications” on page 50).
However, for a synchronous non-array read, the same word of data will be output on
successive clock edges until the burst length requirements are satisfied.
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus. When
the device is operating in synchronous non-array read mode, such as read status, read
ID, or read query, the WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
Refer to the following waveforms for more detailed information: Figure 22,
“Synchronous Single-Word Array or Non-array Read Timing” on page 53, and
Figure 23, “Continuous Burst Read, showing an Output Delay Timing” on page 53, and
Figure 24, “Synchronous Burst-Mode Four-Word Read Timing” on page 54.
5.3
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 7, “Command Bus Cycles” on page 21
shows the bus cycle sequence for each of the supported device commands, while
Table 6, “Command Codes and Definitions” on page 19 describes each command. See
Table 26, “AC Write Specifications” on page 54 for signal-timing details.
When the device is operating in write operations, WAIT is set to a deasserted state as
determined by RCR.10.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
5.4
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
5.5
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5ms time interval, 5μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
Datasheet
17
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
