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JS28F128P30TF75A 参数 Datasheet PDF下载

JS28F128P30TF75A图片预览
型号: JS28F128P30TF75A
PDF下载: 下载PDF文件 查看货源
内容描述: 恒忆Axcell P30-65nm闪存 [Numonyx Axcell P30-65nm Flash Memory]
分类和应用: 闪存
文件页数/大小: 90 页 / 1194 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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P30-65nm SBC  
5.0  
Bus Operations  
CE# low and RST# high enable device read operations. The device internally decodes  
upper address inputs to determine the accessed block. ADV# low opens the internal  
address latches. OE# low activates the outputs and gates selected data onto the I/O  
bus.  
Bus cycles to/from the P30-65nm SBC device conform to standard microprocessor bus  
operations. Table 5, “Bus Operations Summary” summarizes the bus operations and  
the logic levels that must be applied to the device control signal inputs.  
Table 5:  
Bus Operations Summary  
Bus Operation  
RST#  
CLK  
ADV#  
CE#  
OE#  
WE#  
WAIT  
DQ[15:0] Notes  
Asynchronous  
Synchronous  
V
V
V
V
V
X
L
L
L
L
L
L
H
H
L
Output  
Output  
Input  
2
-
IH  
Deasserted  
Driven  
Read  
Write  
Running  
IH  
IH  
IH  
IH  
X
X
X
X
L
L
H
H
X
X
High-Z  
High-Z  
High-Z  
High-Z  
1,2  
2
Output Disable  
Standby  
Reset  
X
X
X
L
H
X
X
High-Z  
High-Z  
High-Z  
H
X
2
V
2,3  
IL  
Notes:  
1.  
Refer to the Table 7, “Command Bus Cycles” on page 21 for valid DQ[15:0] during a write  
operation.  
2.  
3.  
X = Don’t Care (H or L).  
RST# must be at V ± 0.2V to meet the maximum specified power-down current.  
SS  
5.1  
Read - Asynchronous Mode  
To perform an asynchronous page or single word read, an address is driven onto the  
address bus, and CE# is asserted. ADV# can be driven high to latch the address, or it  
must be held low throughout the read cycle. WE# and RST# must already have been  
deasserted. WAIT is set to a deasserted state during asynchronous page mode and  
single word mode as determined by RCR.10. CLK is not used for asynchronous page-  
mode reads, and is ignored. After OE# is asserted, the data is driven onto DQ[15:0]  
after an initial access time tAVQV or tGLQV delay. (See Table 25, “AC Read Specifications”  
on page 50).  
Note:  
If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level,  
WAIT signal can be floated and ADV# must be tied to ground.  
In asynchronous page mode, eight data words are “sensed” simultaneously from the  
flash memory array and loaded into an internal page buffer. The buffer word  
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after  
the initial access delay. The lowest three address bits determine which word of the  
8-word page is output from the data buffer at any given time.  
Refer to the following waveforms for more detailed information:Figure 19,  
“Asynchronous Single-Word Read (ADV# Low)” on page 51, and Figure 20,  
“Asynchronous Single-Word Read (ADV# Latch)” on page 52, and Figure 21,  
“Asynchronous Page-Mode Read Timing” on page 52.  
5.2  
Read - Synchronous Mode  
To perform a synchronous burst read on array or non-array, an initial address is driven  
onto the address bus, and CE# is asserted. WE# and RST# must already have been  
deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately,  
Datasheet  
16  
Apr 2010  
Order Number: 208033-02