P30-65nm SBC
5.6
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
NumonyxTM allow proper CPU initialization following a system reset through the use of
the RST# input.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80.
When RST# is driven low (RST# asserted), the flash device enters reset mode. Then all
internal circuits are de-energized, and the output drivers are placed in High-Z. If RST#
is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no
longer valid. A device reset also clears the Status Register. See Table 18, “Power and
Reset” on page 43 for RST# timing detail.
When RST# is driven high (RST# deasserted), a minimum wait is required before the
flash device is able to perform normal operations. Please consider TPHQV (R5) and
TPHWL (W1) during system design. see Table 25, “AC Read Specifications” on page 50.
and Section 26, “AC Write Specifications” on page 54. After this wake-up interval
passes, normal operation is ready for execution.
Datasheet
18
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
