P30-65nm SBC
Figure 7: QUAD+ SCSP Ballout and Signals (128-Mbit)
Pin 1
1
DU
2
DU
3
4
5
6
7
8
Depop
A19
Depop
VSS
Depop
VCC
RFU
RFU
ADV#
WE#
DQ5
DQ12
DQ4
RFU
VSS
Depop
VCC
CLK
RFU
A20
DU
DU
A
B
C
D
E
F
A
B
C
D
E
F
A4
A18
RFU
A17
A7
A21
A22
A9
A11
A5
RFU
RFU
RFU
RFU
DQ2
DQ1
DQ9
RFU
VCCQ
VSS
A12
A3
VPP
A13
A2
WP#
RST#
DQ10
DQ3
DQ11
RFU
VCC
A10
A14
WAIT
DQ7
DQ15
VCCQ
VSS
A15
A1
A6
A8
A16
G
H
J
A0
DQ8
DQ0
F1-OE#
RFU
VSS
DQ13
DQ14
DQ6
VCC
VSS
F2-CE#
F2-OE#
VCCQ
RFU
VSS
G
H
J
RFU
RFU
F1-CE#
VSS
K
L
K
L
M
DU
DU
Depop
Depop
Depop
Depop
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Control Signals
De-Populated Ball
Reserved for Future Use
Do Not Use
Address
Data
Power/Ground
Legends:
Notes:
1.
2.
3.
4.
A22 is valid for 128-Mbit densities; otherwise, it is a no connect (NC).
A21 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
F2-CE# and F2-OE# are no connect (NC) for all densities.
Unlike TSOP and Easy BGA, A0 is the least significant address bit for the QUAD+ package. Unless otherwise indicated, for
the purpose of brevity, this document will consolidate all later discussions to A1 as the least significant Address bit.
Datasheet
13
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
