P30-65nm SBC
Table 4:
QUAD+ SCSP Signal Descriptions
Symbol
Type
Name and Function
ADDRESS INPUTS: Device address inputs. 128-Mbit: A[22:0].
Note: Unlike TSOP and Easy BGA, A0 is the least significant address bit for the QUAD+ package.
Unless otherwise indicated, for the purpose of brevity, this document will consolidate all discussions
to A1 as the least significant Address bit.
A[MAX:0]
DQ[15:0]
Input
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
Input/
Output
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
Input
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
Flash CHIP ENABLE: Active low input. F1-CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
F1-CE#
CLK
Input
Input
WARNING: Chip enable must be driven high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. F1-OE# low enables the device’s output data buffers during
F1-OE#
RST#
Input
Input
read cycles. F1-OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR.10, WT) determines its polarity when asserted. WAIT’s active output is V or
OL
V
when F1-CE# and F1-OE# are V . WAIT is high-Z if F1-CE# or F1-OE# is V .
OH
I
L
I
H
WAIT
Output
•
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
•
In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
WE#
WP#
Input
Input
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when V ≤ V
. Block erase and program at invalid V
PP
PPLK
PP
voltages should not be attempted.
Set V = V
for in-system program and erase operations. To accommodate resistor or diode drops
PPL
PP
Power/
lnput
VPP
from the system supply, the V level of V can be as low as V
min to perform in-system flash modification. VPP may be 0 V during read operations.
min. V must remain above V
IH
PP
PPL PP PPL
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PPH
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
VCC
Power
when V ≤ V
. Operations at invalid V voltages should not be attempted.
CC
LKO
CC
VCCQ
VSS
Power
Power
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Do Not Use (DU) signal.
RFU
—
DU
NC
—
—
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
NO CONNECT: No internal connection; can be driven or floated.
Datasheet
15
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
