P30-65nm SBC
Table 7:
Command Bus Cycles
First Bus Cycle
(1)
Second Bus Cycle
(1)
Bus
Cycles
Mode
Command
(2)
(2)
Oper
Addr
Data
Oper
Addr
Data
Read Array
1
≥ 2
≥ 2
2
Write
Write
Write
Write
Write
Write
Write
DnA
DnA
DnA
DnA
DnA
WA
0xFF
-
-
-
Read Device Identifier
Read CFI
0x90
0x98
0x70
0x50
0x40
0xE8
Read
Read
Read
-
DBA + IA
ID
Read
DBA + CFI-A
CFI-D
SRD
-
Read Status Register
Clear Status Register
Word Program
DnA
-
1
2
Write
Write
WA
WA
WD
(3)
Buffered Program
> 2
WA
N - 1
Program
Buffered Enhanced
Factory Program
> 2
Write
WA
0x80
Write
WA
0xD0
(4)
(BEFP)
Erase
Block Erase
2
1
Write
Write
BA
0x20
0xB0
Write
-
BA
-
0xD0
-
Program/Erase
Suspend
DnA
Suspend
Program/Erase
Resume
1
Write
DnA
0xD0
-
-
-
Block Lock
2
2
2
2
2
Write
Write
Write
Write
Write
BA
BA
0x60
0x60
0x60
0xC0
0xC0
Write
Write
Write
Write
Write
BA
BA
0x01
0xD0
0x2F
OTP-D
LRD
Block Unlock
Protection
Block Lock-down
Program OTP Register
Program Lock Register
BA
BA
OTP-RA
LRA
OTP-RA
LRA
Configure Read
Configuration
Blank Check
2
2
Write
Write
Write
RCD
BA
0x60
0xBC
0xEB
Write
Write
Write
RCD
BA
0x03
D0
Configuration Register
Block Blank Check
Extended Function
Sub-Op
code
EFI
>2
WA
WA
(5)
Interface
Notes:
1.
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address.
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = OTP Register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[16:1] for TSOP and BGA package; on A[15:0] for QUAD+ package.
2.
3.
ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = OTP Register data.
LRD = Lock Register data.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 256 words of data. Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4.
5.
The confirm command (0xD0) is followed by the buffer data.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1 ≤ N ≤ 256. The subsequent cycles load data
words into the program buffer at a specified address until word count is achieved. After the data words are loaded, the
final cycle is the confirm cycle 0xD0).
Datasheet
21
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
