1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
T
CE
CE#
T
OE
OE#
WE#
T
T
OHZ
OLZ
V
IH
T
T
T
CLZ
OH
CHZ
HIGH-Z
HIGH-Z
DQ
DATA VALID
DATA VALID
7-0
1147 F03.1
Note: AMS = Most significant address
MS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
A
Figure 5: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
T
DH
WP
WE#
T
T
T
AS
DS
WPH
OE#
T
CH
CE#
T
CS
DQ
AA
55
A0
DATA
7-0
SW0
Note: AMS = Most significant address
SW1
SW2
BYTE
(ADDR/DATA)
1147 F04.1
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 6: WE# Controlled Program Cycle Timing Diagram
©2013 Silicon Storage Technology, Inc.
DS25022B
04/13
14
MICROCHIP [ MICROCHIP ]
