1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
T
OEH
T
OES
T
OE
OE#
WE#
Note
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
1147 F07.1
Note: Toggled bit output is always high first.
A
A
MS = Most significant address
MS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 9: Toggle Bit Timing Diagram
T
SIX-BYTE CODE FOR SECTOR-ERASE
SE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
30
DQ
7-0
SW5
1147 F08.1
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. (See Table 10)
SAXX = Sector Address
Toggled bit output is always high first.
AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 10:WE# Controlled Sector-Erase Timing Diagram
©2013 Silicon Storage Technology, Inc.
DS25022B
04/13
16
MICROCHIP [ MICROCHIP ]
